? semiconductor components industries, llc, 2011 may, 2011 ? rev. 12 1 publication order number: mc74hc374a/d mc74hc374a octal 3-state non-inverting d flip-flop high ? performance silicon ? gate cmos the mc74hc374a is identical in pinout to the ls374. the device inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with lsttl outputs. data meeting the setup time is clocked to the outputs with the rising edge of the clock. the output enable input does not affect the states of the flip ? flops, but when output enable is high, the outputs are forced to the high ? impedance state; thus, data may be stored even when the outputs are not enabled. the hc374a is identical in function to the hc574a which has the input pins on the opposite side of the package from the output. this device is similar in function to the hc534a which has inverting outputs. features ? output drive capability: 15 lsttl loads ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 2.0 to 6.0 v ? low input current: 1.0 a ? high noise immunity characteristic of cmos devices ? in compliance with the requirements defined by jedec standard no. 7 a ? chip complexity: 266 fets or 66.5 equivalent gates ? these devices are pb ? free and are rohs compliant http://onsemi.com 20 1 1 20 marking diagrams soic ? 20 dw suffix case 751d 74hc374a awlyywwg hc 374a alyw tssop ? 20 dt suffix case 948e soeiaj ? 20 f suffix case 967 74hc374a awlywwg 1 1 1 20 1 20 20 20 see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information pdip ? 20 n suffix case 738 1 20 mc74hc374an awlyywwg 1 20 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g or = pb ? free package (note: microdot may be in either location)
mc74hc374a http://onsemi.com 2 logic diagram data inputs d0 11 clock d1 d2 d3 d4 d5 d6 d7 18 17 14 13 8 7 4 3 1 output enable 19 q0 q1 q2 q3 q4 q5 q6 q7 16 15 12 9 6 5 2 pin 20 = v cc pin 10 = gnd noninverting outputs function table inputs output output enable clock d q lhh lll l l,h, x no change hxxz x = don?t care z = high impedance pin assignment q2 d1 d0 q0 output enable gnd q3 d3 d2 q1 5 4 3 2 1 10 9 8 7 6 14 15 16 17 18 19 20 11 12 13 q6 d6 d7 q7 v cc clock q4 d4 d5 q5 ordering information device package shipping ? mc74hc374ang pdip ? 20 (pb ? free) 18 units / box mc74hc374adwg soic ? 20 wide (pb ? free) 38 units / rail mc74hc374adwr2g soic ? 20 wide (pb ? free) 1000 tape & reel MC74HC374ADTG tssop ? 20* 75 units / rail mc74hc374adtr2g tssop ? 20* 2500 tape & reel mc74hc374afg soeiaj ? 20 (pb ? free) 40 units / rail mc74hc374afelg soeiaj ? 20 (pb ? free) 2000 tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *this package is inherently pb ? free.
mc74hc374a http://onsemi.com 3 maximum ratings symbol parameter value unit v cc dc supply voltage (referenced to gnd) ? 0.5 to + 7.0 v v in dc input voltage (referenced to gnd) ? 0.5 to v cc + 0.5 v v out dc output voltage (referenced to gnd) ? 0.5 to v cc + 0.5 v i in dc input current, per pin 20 ma i out dc output current, per pin 35 ma i cc dc supply current, v cc and gnd pins 75 ma p d power dissipation in still air, plastic dip? soic package? tssop package? 750 500 450 mw t stg storage temperature ? 65 to + 150 c t l lead temperature, 1 mm from case for 10 seconds (plastic dip, soic, ssop or tssop package) 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recom mended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. ?derating ? plastic dip: ? 10 mw/ c from 65 to 125 c soic package: ? 7 mw/ c from 65 to 125 c tssop package: ? 6.1 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 2.0 6.0 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types ? 55 + 125 c t r , t f input rise and fall time v cc = 2.0 v (figure 1) v cc = 4.5 v v cc = 6.0 v 0 0 0 1000 500 400 ns dc electrical characteristics (voltages referenced to gnd) symbol parameter test conditions v cc v guaranteed limit unit ? 55 to 25 c 85 c 125 c v ih minimum high ? level input voltage v out = 0.1 v or v cc ? 0.1 v |i out | 20 a 2.0 3.0 4.5 6.0 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 v v il maximum low ? level input voltage v out = 0.1 v or v cc ? 0.1 v |i out | 20 a 2.0 3.0 4.5 6.0 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 v v oh minimum high ? level output voltage v in = v ih or v il |i out | 20 a 2.0 4.5 6.0 1.90 4.40 5.90 1.90 4.40 5.90 1.90 4.40 5.90 v v in = v ih or v il |i out | 2.4 ma |i out | 6.0 ma |i out | 7.8 ma 3.0 4.5 6.0 2.48 2.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 v v ol maximum low ? level output voltage v in = v ih or v il |i out | 20 a 2.0 4.5 6.0 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 v v in = v ih or v il |i out | 2.4 ma |i out | 6.0 ma |i out | 7.8 ma 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 v i in maximum input leakage current v in = v cc or gnd 6.0 0.1 1.0 1.0 a this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high ? impedance cir- cuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
mc74hc374a http://onsemi.com 4 dc electrical characteristics (voltages referenced to gnd) symbol unit guaranteed limit v cc v test conditions parameter symbol unit 125 c 85 c ? 55 to 25 c v cc v test conditions parameter i oz maximum three ? state leakage current output in high ? impedance state v in = v il or v ih v out = v cc or gnd 6.0 0.5 5.0 10 a i cc maximum quiescent supply current (per package) v in = v cc or gnd i out = 0 a 6.0 4 40 160 a ac electrical characteristics (c l = 50 pf, input t r = t f = 6.0 ns) symbol parameter v cc v guaranteed limit unit ? 55 to 25 c 85 c 125 c f max maximum clock frequency (50% duty cycle) 2.0 3.0 4.5 6.0 6 15 30 35 5 10 24 28 4 8 20 24 mhz t plh t phl maximum propagation delay, input clock to q (figures 1 and 5) 2.0 3.0 4.5 6.0 125 80 25 21 155 110 31 26 190 130 38 32 ns t plz t phz maximum propagation delay, output enable to q (figures 3 and 6) 2.0 3.0 4.5 6.0 150 100 30 26 190 125 38 33 225 150 45 38 ns t pzl t pzh maximum propagation delay, output enable to q (figures 3 and 6) 2.0 3.0 4.5 6.0 150 100 30 26 190 125 38 33 225 150 45 38 ns t tlh t thl maximum output transition time, any output (figures 1 and 5) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 16 110 36 22 19 ns c in maximum input capacitance 10 10 10 pf c out maximum three ? state output capacitance (output in high ? impedance state) 15 15 15 pf c pd power dissipation capacitance (per enabled output)* typical @ 25 c, v cc = 5.0 v pf 34 * used to determine the no ? load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc .
mc74hc374a http://onsemi.com 5 timing requirements (c l = 50 pf, input t r = t f = 6.0 ns) symbol parameter figure v cc volts guaranteed limit unit ? 55 to 25 c 85 c 125 c min max min max min max t su minimum setup time, data to clock 3 2.0 3.0 4.5 6.0 50 40 10 9 65 50 13 11 75 60 15 13 ns t h minimum hold time, clock to data 3 2.0 3.0 4.5 6.0 5.0 5.0 5.0 5.0 5.0 5 0 5.0 5.0 5.0 5.0 5.0 5.0 ns t w minimum pulse width, clock 1 2.0 3.0 4.5 6.0 60 23 12 10 75 27 15 13 90 32 18 15 ns t r , t f maximum input rise and fall times 1 2.0 3.0 4.5 6.0 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns switching waveforms figure 1. t r t f v cc gnd t thl t tlh 90% 50% 10% 90% 50% 10% clock t plh t phl q t w 1/f max 50% 50% 50% output enable q t pzl t plz t pzh t phz 10% 90% v cc gnd high impedance v ol v oh high impedance 50% data clock v cc v cc gnd gnd valid t h t su 50% q figure 2. figure 3.
mc74hc374a http://onsemi.com 6 test circuits figure 4. *includes all probe and jig capacitance c l * test point device under test output *includes all probe and jig capacitance c l * test point device under test output connect to v cc when testing t plz and t pzl . connect to gnd when testing t phz and t pzh . 1 k figure 5. figure 6. expanded logic diagram d0 3 dq c q0 2 d1 4 dq c q1 5 d2 7 dq c q2 6 d3 8 dq c q3 9 d4 13 dq c q4 12 d5 14 dq c q5 15 d6 17 dq c q6 16 d7 18 dq c q7 19 clock output enable 11 1
mc74hc374a http://onsemi.com 7 package dimensions pdip ? 20 n suffix plastic dip package case 738 ? 03 issue e notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension b does not include mold flash. m l j 20 pl m b m 0.25 (0.010) t dim min max min max millimeters inches a 25.66 27.17 1.010 1.070 b 6.10 6.60 0.240 0.260 c 3.81 4.57 0.150 0.180 d 0.39 0.55 0.015 0.022 g 2.54 bsc 0.100 bsc j 0.21 0.38 0.008 0.015 k 2.80 3.55 0.110 0.140 l 7.62 bsc 0.300 bsc m 0 15 0 15 n 0.51 1.01 0.020 0.040 e 1.27 1.77 0.050 0.070 1 11 10 20 ? a ? seating plane k n f g d 20 pl ? t ? m a m 0.25 (0.010) t e b c f 1.27 bsc 0.050 bsc soic ? 20 dw suffix case 751d ? 05 issue g 20 1 11 10 b 20x h 10x c l 18x a1 a seating plane h x 45 e d m 0.25 m b m 0.25 s a s b t e t b a dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 12.65 12.95 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of b dimension at maximum material condition.
mc74hc374a http://onsemi.com 8 package dimensions tssop ? 20 dt suffix case 948e ? 02 issue c dim a min max min max inches 6.60 0.260 millimeters b 4.30 4.50 0.169 0.177 c 1.20 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.27 0.37 0.011 0.015 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . 110 11 20 pin 1 ident a b ? t ? 0.100 (0.004) c d g h section n ? n k k1 jj1 n n m f ? w ? seating plane ? v ? ? u ? s u m 0.10 (0.004) v s t 20x ref k l l/2 2x s u 0.15 (0.006) t detail e 0.25 (0.010) detail e 6.40 0.252 --- --- s u 0.15 (0.006) t 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint
mc74hc374a http://onsemi.com 9 package dimensions soeiaj ? 20 f suffix case 967 ? 01 issue a dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.15 0.25 0.006 0.010 12.35 12.80 0.486 0.504 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.81 --- 0.032 a 1 h e q 1 l e 10 0 10 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). h e a 1 l e q 1 c a z d e 20 110 11 b m 0.13 (0.005) e 0.10 (0.004) view p detail p m l a b c d e e l m z on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. mc74hc374a/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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